It is desirable to be able to measure mismatch in digital logic path delay variations. Current techniques employ ring oscillators (RO). RO-based approaches generally employ too many stages to accurately represent realistic path lengths in actual circuits. If the RO does have the correct number of stages, it does not have the correct slew rates. Furthermore, RO-based approaches do not account for clock skew and/or jitter at the latches at the beginning and/or end of the delay path (because there are no latches in ROs), and RO-based approaches do not generally represent actual logic gates with correct fan-outs, threshold voltages, combination(s) of logic gates, and the like. In addition, ROs are run one at a time, and measured one at a time, and ROs require a high-speed output pad for frequency measurement. Measurement of ROs averages together many passes through the logic path, e.g., a 1 ms measurement of a 1 GHz ring implies 106 passes, which may average out some inherent variation of the path delay.